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ds07-13604-2e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16l MB90660A series mb90662a/663a/p663a n description MB90660A series microcontrollers are 16-bit microcontrollers optimized for high speed realtime processing of consumer equipment and system control of air conditioner video cameras, vcrs, and copiers. based on the f 2 mc*-16 cpu core, an f 2 mc-16l is used as the cpu. this cpu includes high-level language-support instructions and robust task switching instructions, and additional addressing modes. microcontrollers in this series have built-in peripheral resources including multi-function timers, 16-bit reload timer four channels, 8-bit pwm one channel, uart one channel, 10-bit a/d eight converter channels, and external interrupt eight channels. *: f 2 mc stands for fujitsu flexible microcontroller. n features ?f 2 mc-16l cpu ? minimum execution time: 62.5 ns/4 mhz oscillation (uses pll multiplier): fastest speed at quadruple operation ? instruction set optimized for controller applications upward compatibility at object level with the f 2 mc-16(h) various data types (bit, byte, word, long-word) higher speed due to review of instruction cycle expanded addressing modes: 23 types high coding efficiency two access methods (bank system or linear pointer) improved multiply-and-divide instructions (additional signed instructions) improved high-precision operation with 32-bit accumulator extended intelligent i/o services (access area extended by 64 kbytes) large memory space: 16 mbytes (continued) n pac k ag e 64-pin plastic sh-dip (dip-64p-m01) 64-pin plastic lqfp (fpt-64p-m09)
2 MB90660A series (continued) ? improved instruction set applicable to high-level language (c) and multitasking system stack pointer improved indirect instructions using various pointers barrel shift instruction stack check function ? improved execution speed: 4-byte instruction queue ? improved interrupt functions ? automatic data transfer function independent of cpu peripheral resources ? rom: 16 kbytes (mb90661a) 32 kbytes (mb90662a) 48 kbytes (mb90663a) one-time prom: 48 kbytes (mb90p663a) ? ram: 512 bytes (mb90661a) 1.64 kbytes (mb90662a) 2 kbytes (mb90663a/mb90p663a) ? general-purpose ports: max. 51 ? uart: 1 channel can be used for both asynchronous transfer and clocked serial (i/o extended serial) communications ? a/d converter: 10-bit, 8 channels includes 8-bit conversion mode ? 16-bit reload timer: 4 channels ? 8-bit pwm: 1 channel ? external interrupts: 8 channels ? 18-bit timebase timer with watchdog timer function ? pll clock multiplier function ? cpu intermittent operation function ? various standby modes ? package: sh-dip-64/lqfp-64 (0.65-mm pitch) ? cmos technology
3 MB90660A series n product lineup mb90p663a mb90662a mb90663a classification otprom mask rom mask rom rom size 48 kbytes 32 kbytes 48 kbytes ram size 2 kbytes 1.64 kbytes 2 kbytes cpu functions number of basic instructions : 340 instruction bit length : 8/16 bits instruction length : 1 to 7 bytes data bit length : 1, 4, 8, 16, or 32 bits minimum execution time : 62.5 ns/4 mhz (pll 4 multiply) interrupt processing time : 1000 ns/16 mhz (minimum) por ts input por ts : 4 i/o ports (cmos) : 39 i/o ports (n channel open-drain) : 8 to t a l : 5 1 packages dip-64p-m01 fpt-64p-m09 dip-64p-m01 fpt-64p-m09 dip-64p-m01 fpt-64p-m09 multi-function timer 14-bit up/down count timer 1, buffered compare register 4, buffered compare clear register, zero detect terminal control, 4 output channels, non-overlapped 3-phase waveform output, 3-phase independent dead time timer, 4-bit carrier counter uart full duplex double buffer selectable clock synchronous/asynchronous operation built-in dedicated baud rate generator (during asynchronous operation: 62500, 31250, 19230, 9615, 4808, 2404, 1202 bps) a/d converter 10-bit precision 8 channels a/d conversion time : 6.13 m s (98 machine cycles at 16 mhz machine clock, includes sample hold time) startup trigger : startup by software, external source, or multi-function timer output (rt0) can be selected activiation : single, scan (multiple channel continuous), continuous (1 channel continuous), stop (synchronized with conversion start in scan mode) 16-bit reload timer 16-bit reload timer operation (toggle output, one-shot output selectable) (count clock can be selected from 0.125 m s, 0.5 m s, or 2.0 m s at 16 mhz machine cycle) event count function selectable 4 channels built-in 8-bit pwm 8-bit resolution pwm operation (arbitrary cycle: duty ratio pulse output) (count clock can be selected from 0.125 m s or 64.0 m s at 16 mhz machine cycle) external interrupts number of inputs: 8 external interrupt mode (interrupts can be generated by four types of request detect sources) pll function 1/2/3/4-time multiplier can be selected (please set so as not to exceed guaranteed operation frequency) miscellaneous items v pp is shared with md2 terminal (when writing the eprom) part number parameter
4 MB90660A series n pin assignment 1 p66/rt0 2 dtti 3 p40/sin 4 p41/sot 5 p42/sck 6 p43/pwm 7 p44/int0 8 p45/int1 9 p46/int2/trg 10 p47/int3/atg 11 p50/an0 12 p51/an1 13 p52/an2 14 p53/an3 15 p54/an4 16 p55/an5 17 p56/an6 18 p57/an7 19 av cc 20 avr 21 av ss 22 p30 23 p31 24 p32 v cc p65/z p64/y p63/x p62/rt3/w p61/rt2/v p60/rt1/u v ss p27/tim3/int7 p26/tim2/int6 p25/tim1/int5 p24/tim0/int4 p23 p22 p21 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 p20 p17 p16 p15 p14 p13 p12 p11 p10 49 48 47 46 45 44 43 42 41 25 p33 26 md0 27 rst 28 md1 29 md2 30 x0 31 x1 32 v ss p07 p06 p05 p04 p03 p02 p01 p00 40 39 38 37 36 35 34 33 (dip-64p-m01) (top view)
5 MB90660A series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p46/int2/trg p47/int3/atg p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 av cc avr av ss p30 p31 p32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/tim3/int7 p26/tim2/int6 p25/tim1/int5 p24/tim0/int4 p23 p22 p21 p20 p17 p16 p15 p14 p13 p12 p11 p10 md1 md2 x0 x1 v ss p00 p01 p02 p03 p04 p05 p06 p07 p43/pwm p42/sck p41/sot p40/sin dtti p66/rt0 v cc p65/z p64/y p63/x p62/rt3/w p61/rt2/v p60/rt1/u v ss p44/int0 p45/int1 p33 md0 rst (fpt-64p-m09) (top view)
6 MB90660A series n pin description (continued) *1: dip-64p-m01 *2: fpt-64p-m09 pin no. pin name circuit type function sh-dip* 1 lqfp* 2 30 22 x0 a (oscillator) crystal oscillator pin (32 mhz). 31 23 x1 33 to 40 25 to 32 p00 to p07 b (cmos) general-purpose i/o ports. 41 to 48 33 to 40 p10 to p17 b (cmos) general-purpose i/o ports. 49 to 52 41 to 44 p20 to p23 b (cmos) general-purpose i/o ports. 53 to 56 45 to 48 p24 to p27 g (cmos) general-purpose i/o ports. this function is activated when the output specification of the reload timer is disabled. tim0 to tim3 i/o pins for reload timers 0 to 4. input is used only as necessary while serving as input for the reload timer. it is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. their function as output terminals for the reload timer is activated when the output specification is enabled. int4 to int7 external interrupt request input pins. input is used only as necessary while external interrupts are enabled. it is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. 22 to 25 14 to 17 p30 to p33 b (cmos) general-purpose i/o ports. 359p40 e (cmos/h) general-purpose i/o port. this function is always enabled. sin uart serial data input pin. input is used only as necessary while serving as uart input. it is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. 460p41 e (cmos/h) general-purpose i/o port. this function is activated when the serial data output specification of the uart is disabled. sot uart serial data output pin. this function is activated when the serial data output specification of the uart is enabled.
7 MB90660A series (continued) *1: dip-64p-m01 *2: fpt-64p-m09 pin no. pin name circuit type function sh-dip* 1 lqfp* 2 561p42 e (cmos/h) general-purpose i/o port. this function is activated when the clock output specification of the uart is disabled. sck uart clock i/o pin. this function is activated when the clock output specification of the uart is enabled. input is used only as necessary while serving as uart input. it is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. 662p43 e (cmos/h) general-purpose i/o port. this function is activated when the output specification of the pwm is disabled. pwm pwm timer output pin. this function is activated when the waveform output specifica- tion of the pwm timer is enabled. 7 8 63 64 p44 to p45 d (cmos/h) general-purpose i/o ports. this function is always active. int0 to int1 external interrupt request input pins. input is used only as necessary while external interrupts are enabled. 91p46 d (cmos/h) general-purpose input port. this function is always active. int2 external interrupt request input pin. input is used only as necessary while external interrupts are enabled. trg timer clear trigger input pin for multi-function timer. input is used only as necessary while multi-function timer input is enabled. 10 2 p47 d (cmos/h) general-purpose input port. this function is always active. int3 external interrupt request input pin. input is used only as necessary while external interrupts are enabled. at g trigger input pin for the a/d converter. input is used only as necessary while the a/d converter is performing input. 11 to 18 3 to 10 p50 to p57 c (ad) open-drain type i/o ports. this function is enabled when the analog input enable register specification is port. an0 to an7 analog input pins for the a/d converter. this function is enabled when the analog input enable register specification is ad.
8 MB90660A series (continued) *1: dip-64p-m01 *2: fpt-64p-m09 pin no. pin name circuit type function sh-dip* 1 lqfp* 2 58 50 p60 e (cmos/h) general-purpose i/o port. this function is enabled when the multi-function timer waveform output specification is disabled and the 3-phase waveform output specification is disabled. rt1 multi-function timer waveform output pin. this function is enabled when the multi-function timer output specification is enabled. u 3-phase waveform output pin. this function is enabled when the 3-phase waveform output specification is enabled. 59 51 p61 e (cmos/h) general-purpose i/o port. this function is enabled when the multi-function timer waveform output specification is disabled and the 3-phase waveform output specification is disabled. rt2 multi-function timer waveform output pin. this function is enabled when the multi-function timer output specification is enabled. v 3-phase waveform output pin. this function is enabled when the 3-phase waveform output specification is enabled. 60 52 p62 e (cmos/h) general-purpose i/o port. this function is enabled when the multi-function timer waveform output specification is disabled and the 3-phase waveform output specification is disabled. rt3 multi-function timer waveform output pin. this function is enabled when the multi-function timer output specification is enabled. w 3-phase waveform output pin. this function is enabled when the 3-phase waveform output specification is enabled. 61 53 p63 e (cmos/h) general-purpose i/o port. this function is enabled when the 3-phase waveform output specification is disabled. x 3-phase waveform output pin. this function is enabled when the 3-phase waveform output specification is enabled. 62 54 p64 e (cmos/h) general-purpose i/o port. this function is enabled when the 3-phase waveform output specification is disabled. y 3-phase waveform output pin. this function is enabled when the 3-phase waveform output specification is enabled.
9 MB90660A series (continued) *1: dip-64p-m01 *2: fpt-64p-m09 pin no. pin name circuit type function sh-dip* 1 lqfp* 2 63 55 p65 e (cmos/h) general-purpose i/o port. this function is enabled when the 3-phase waveform output specification is disabled. z 3-phase waveform output pin. this function is enabled when the 3-phase waveform output specification is enabled. 157p66 e (cmos/h) general-purpose i/o port. this function is enabled when the multi-function timer waveform output specification is disabled. rt0 multi-function timer waveform output pin. this function is enabled when the multi-function timer output specification is enabled. 258dtti d (cmos/h) 3-phase waveform output disable input (dtti) pin. 19 11 av cc power supply power supply for analog circuits. turn this power supply on/off by applying a voltage level greater than av cc to v cc . 20 12 avr power supply reference power supply for analog circuits. turn this pin on/off by applying a voltage level greater than avr to av cc . 21 13 av ss power supply ground level for analog circuits. 26 28 29 18 20 21 md0 to md2 f (cmos/h) input pins for specifying operation mode. use these pins by directly connecting to v cc or v ss . 27 19 rst d (cmos/h) external reset request input pin. 64 56 v cc power supply power supply for digital circuits. 32 57 24 49 v ss power supply ground level for digital circuits.
10 MB90660A series n i/o circuit type (continued) type circuit remarks a ? 3 mhz to 32 mhz operation ? oscillation feedback resistor: approx. 1 m? b ? cmos level input and output with standby control ? pull-up option can be selected with standby control c ? n-channel open-drain output cmos level hysteresis input with a/d control d ? cmos level hysteresis input without standby control ? pull-up option can be selected without standby control x1 x0 standby control signal clock input standby control signal digital input digital output digital output a/d disable digital input digital output a/d input digital input
11 MB90660A series (continued) type circuit remarks e ? cmos level output ? cmos level hysteresis input with standby control ? pull-up option can be selected with standby control f ? cmos level input (mask rom version uses cmos hysteresis input) without standby control ? pull-up option can be selected for md2 (*1) pull-up option can be selected for md1/0 (*2) both without standby option ? the mb90p663a does not include a noise filter. it also does not have a p channel protect tr (*3) for the md2 pin or pull-down. g ? cmos level input and output without standby control ? pull-up option can be selected with standby control standby control signal digital input digital output digital output digital input noise filter typ. 40 ns *1 *2 *3 digital input digital output digital output
12 MB90660A series n handling devices 1. preventing latchup latchup may occur with cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. to prevent the similar aftereffects, use also the utmost care not to allow the analog supply voltage to exceed the digital supply voltage. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be pins should be connected to a pull- up or pull-down resistor. 3. external reset input when resetting by inputting l level to the rst pin, the l level must be input for at least 5 machine cycles to ensure that internal reset has occurred. be aware of this point when using external clock input. 4. v cc , v ss pin be sure that both v cc and v ss are at the same voltage. 5. notes on using an external clock drive x0 when using an external clock. 6. order of power-on to a/d converter and analog inputs power-off (av cc , avr) to the digital power supply (v cc ) must be performed only after the a/d converter and the analog inputs (an0 to an7) has been turned on. turning on or off should always be performed keeping avr below av cc . use caution for the input voltage not to exceed av cc when the pin sharing the analog input for its function is used as an input port. 7. programming mode when the mb90p663a is shipped from fujitsu, all bits (48 k 8 bits) are set to 1. program by setting selected bits to 0 when you wish to set the data. note that 1 cannot be programming electrically. x0 x1 MB90660A ? using an external clock
13 MB90660A series 8. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 9. programming yields all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 10.fluctuations in supply voltage although the assured v cc supply voltage operating range is as specified, sudden fluctuations even within this range may cause a malfunction. therefore, the voltage supply to the ic should be kept as constant as possible. the v cc ripple (p-p value) at the supply frequency (50 to 60 hz) should be less than 10% of the typical v cc value, or the coefficient of excessive variation should not be more than 0.1 v/ms instantaneous change when power is supplied. program and verify aging 150 c, 48 h data verification assembly
14 MB90660A series n programming the mb90p663a eprom since the mb90p663a is functionally equivalent to the mbm27c1000 when it is in eprom mode, it is possible to program them with a general-purpose eprom programmer by using a special adaptor socket. however, the MB90660A does not support the electronic signature (device id code) mode. 1. pin assignment in eprom mode ? mbm27c1000-compatible pins ? power supply, gnd connection pins mbm27c1000 mb90p663a mbm27c1000 mb90p663a pin no. pin name pin no. pin name pin no. pin name pin no. pin name sh-dip lqfp sh-dip lqfp 1v pp 29 21 md2 (v pp )32 v cc 64 56 v cc 2oe 24 16 p32 31 pgm 25 17 p33 3 a15 48 40 p17 30 nc 4 a12 45 37 p14 29 a14 47 39 p16 5 a07 56 48 p27 28 a13 46 38 p15 6 a06 55 47 p26 27 a08 41 33 p10 7 a05 54 46 p25 26 a09 42 34 p11 8 a04 53 45 p24 25 a11 44 36 p13 9 a03 52 44 p23 24 a16 22 14 p30 10 a025143p22 23 a104335p12 11 a01 50 42 p21 22 ce 23 15 p31 12 a00 49 41 p20 21 d07 40 32 p07 13 d00 33 25 p00 20 d06 39 31 p06 14 d01 34 26 p01 19 d05 38 30 p05 15 d02 35 27 p02 18 d04 37 29 p04 16 gnd 17 d03 36 28 p03 type pin no. pin name sh-dip lqfp power 2 64 58 56 dtti v cc gnd 57 21 27 32 26 3 4 5 49 13 19 24 18 59 60 61 v ss av ss rst v ss md0 p40 p41 p42
15 MB90660A series ? pins other than mbm27c1000-compatible pins 2. eprom programmer socket adapter and recommended programmer manufacturer inquiry: sun hayato co., ltd.: tel (81)-3-3986-0403 fax (81)-3-5396-9106 minato electronics inc.: tel: usa (1)-916-348-6066 japan (81)-45-591-5611 data i/o co., ltd.: tel: usa/asia (1)-206-881-6444 europe (49)-8-985-8580 advantest corp.: tel: except japan (81)-3-3930-4111 pin no. pin name processing sh-dip lqfp 30 28 22 20 x0 md1 pull-up by 4.7 k w 31 23 x1 open 9 10 11 to 18 19 20 58 to 63 1 6 to 8 1 2 3 to 10 11 12 50 to 55 57 62 to 64 p46 p47 p50 to p57 av cc avr p60 to p65 p66 p43 to p45 part no. package compatible socket adapter sun hayato co., ltd. recommended programmer manufacturer and programmer name minato electronics inc. data i/o co., ltd. advantest corp. mb90p663ap sh-dip-64 rom-64sd-32dp-16l recommended recommended recommended mb90p663apf lqfp-64 rom-64sf-32dp-16l recommended recommended recommended 1 m w -level pull-up resistor connected to each pin
16 MB90660A series 3. programming data (1) adjust the eprom programmer to settings for the mbm27c1000. (2) load program data from addresses 10000 h to 1ffff h in the eprom programmer. otprom addresses ff4000 h to ffffff h of the mb90p663a in operation mode correspond to addresses 14000 h to 1ffff h in eprom mode. (3) set the mb90p663a into the adaptor socket and install the adaptor socket into the eprom programmer. pay attention to the orientation of the device and the adaptor socket at this time. (4) programming data to the eprom. (5) if data cannot be programmed, try again with a 0.1 m f capacitor connected between v cc and gnd and v pp and gnd. note: since mask rom products (mb90662a/663a) do not include an eprom mode, data cannot be read-out using an eprom programmer. ffffff h ff4000 h ff0000 h 10000 h 1ffff h operation mode eprom mode otprom otprom 14000 h
17 MB90660A series 4. prom option bitmap the programming method is the same as a prom, and can be set by programming values to addresses indicated in the memory map. the following bit map shows the relation between bits and options. ? prom option bitmap initially (value when blank), all bits are 1. *1: under this release, the pull-up resistor is cut-off during stop mode for pins for which the pull-up option was selected. (pins for which the circuit type shown in the n pin description is b or e.) however, the pull-up resistor is not cut-off even in stop mode for p44 to 47, rst , dtti (pins for which the circuit type shown in the n pin description is d or g), and md1 and md0. *2: whether or not a pull-up/pull-down resistor is present for md2, md1 and md0 is determined as follows. if pull- up/pull-down resistor is selected, it is included with all 2 (or 3) pins. presence or absence of the pull-up or pull- down resistors for the mode terminal cannot be selected for each pin. notes: ? ff h must be set to addresses no defined in the table above. ? since the option setting for the mb90p663a takes 8 machine cycles, the option setting is not made until a clock is provided after power-on. (this results in no pull-up for all pins, and asynchronous reset input is accepted.) 76543210 00004 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 00008h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0000ch p27 pull-up 1: no 0: yes p26 pull-up 1: no 0: yes p25 pull-up 1: no 0: yes p24 pull-up 1: no 0: yes p23 pull-up 1: no 0: yes p22 pull-up 1: no 0: yes p21 pull-up 1: no 0: yes p20 pull-up 1: no 0: yes 00010h p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 00014h * 1 p47 pull-up 1: no 0: yes p46 pull-up 1: no 0: yes p45 pull-up 1: no 0: yes p44 pull-up 1: no 0: yes rst pull-up 1: no 0: yes dtti pull-up 1: no 0: yes accept asyn- chronous reset 1: yes 0: no md1/md0 *2 pull-up 1: no 0: yes 00018h open p66 pull-up 1: no 0: yes p65 pull-up 1: no 0: yes p64 pull-up 1: no 0: yes p63 pull-up 1: no 0: yes p62 pull-up 1: no 0: yes p61 pull-up 1: no 0: yes p60 pull-up 1: no 0: yes pin mb90p663a mb90663a/2a md2 no pull-down can be selected md1 with pull-up resistor with pull-up resistor md0 with pull-up resistor with pull-up resistor bit address
18 MB90660A series n block diagram clock controller ram cpu f 2 mc-16l family core external interrupts rom 16-bit timer 8-bit pwm pwm x0, x1 rst md0 to md2 tim0 to tim3 i/o ports 8 8 8 4 8 8 7 p00 to p07 p10 to p17 p20 to p27 p30 to p33 p40 to p47 p50 to p57 p60 to p66 10-bit a/d converter avcc avr avss an0 to an7 atg uart sin sot sck interrupt controller trg dtti rt0 to rt3 u, v, w x, y, z int0 to int7 multi-function timer (dead time timer) note: in the diagram above, i/o ports share pins with all internal function blocks. these cannot be used as i/o ports when used as internal module pins. f 2 mc-16 bus
19 MB90660A series n f 2 mc-16l cpu programming model ah al dpr pcb dtb usb ssb adb 8 bits 16 bits 32 bits accumulator usp ssp ps pc user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register 32 banks max. r7 r6 r5 r4 r3 r2 r1 r0 rw3 rw2 rw1 rw0 16 bits 000180 h + rp * 10 h ? rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 ilm rp i s t n z v c ccr ? dedicated registers ? processor states (ps) ? general-purpose registers
20 MB90660A series n memory map ffffff h address1# ff0000 h 010000 h address2# 000380 h 004000 h address3# 000180 h 000100 h 0000c0 h 000000 h single chip rom area rom area (ff bank image) ram registers peripheral resources 002000 h : internal : access disabled product model address #1 address #2 address #3 mb90662a ff8000 h 008000 h 000780 h mb90663a ff4000 h 004000 h 000900 h mb90p663a ff4000 h 004000 h 000900 h
21 MB90660A series n i/o map (continued) address register name access *2 resource name initial value 000000 h port 0 data register pdr0 r/w* port 0 xxxxxxxx 000001 h port 1 data register pdr1 r/w* port 1 xxxxxxxx 000002 h port 2 data register pdr2 r/w* port 2 xxxxxxxx 000003 h port 3 data register pdr3 r/w* port 3 C C C C x x x x 000004 h port 4 data register pdr4 r/w! port 4 xxxxxxxx 000005 h port 5 data register pdr5 r/w* port 5 11111111 000006 h port 6 data register/ port data buffer register pdr6/ pdbr r/w* port 6 Cxxxxxxx 000007 h to 0f h vacancy *1 000010 h port 0 direction register ddr0 r/w port 0 0 0 000000 000011 h port 1 direction register ddr1 r/w port 1 0 0 000000 000012 h port 2 direction register ddr2 r/w port 2 0 0 000000 000013 h port 3 direction register ddr3 r/w port 3 C C CC0000 000014 h port 4 direction register ddr4 r/w port 4 C C CC0000 000015 h analog input enable register ader r/w port 5 11111111 000016 h port 6 direction register ddr6 r/w port 6 C 0 000000 000017 h to 1b h vacancy *1 00001c h to 1f h system reserved area *1 000020 h pwm operation mode control register pwmc r/w pwm 00000CC1 000021 h vacancy *1 000022 h pwm reload register prll r/w xxxxxxxx 000023 h prlh r/w xxxxxxxx 000024 h serial mode register smr r/w! uart 00000C00 000025 h serial control register scr r/w! 00000100 000026 h serial input data register/ serial output data register sidr/ sodr r/w xxxxxxxx 000027 h serial status register ssr r/w! 00001C00 000028 h interrupt enable register enir r/w external interrupt 00000000 000029 h interrupt source register eirr r/w external interrupt xxxxxxxx 00002a h request level setting register elvr r/w 00000000 00002b h 00000000 00002c h a/d control status register adcs r/w! a/d converter 00000000 00002d h 00000000
22 MB90660A series (continued) (continued) address register name access *2 resource name initial value 00002e h a/d data register adcr r/w! a/d converter xxxxxxxx 00002f h 000000xx 000030 h control status register tmcsr0 r/w 16-bit reload timer 0 00000000 000031 h CCCC0000 000032 h 16-bit timer register/ 16-bit reload register tmr0/ tmrlr0 r/w xxxxxxxx 000033 h xxxxxxxx 000034 h control status register tmcsr1 r/w 16-bit reload timer 1 00000000 000035 h CCCC0000 000036 h 16-bit timer register/ 16-bit reload register tmr1/ tmrlr1 r/w xxxxxxxx 000037 h xxxxxxxx 000038 h control status register tmcsr2 r/w 16-bit reload timer 2 00000000 000039 h CCCC0000 00003a h 16-bit timer register/ 16-bit reload register tmr2/ tmrlr2 r/w xxxxxxxx 00003b h xxxxxxxx 00003c h control status register tmcsr3 r/w 16-bit reload timer 3 00000000 00003d h CCCC0000 00003e h 16-bit timer register/ 16-bit reload register tmr3/ tmrlr3 r/w xxxxxxxx 00003f h xxxxxxxx 000040 h timer control status register tcsr r/w! multi-function timer 10000000 000041 h compare interrupt control register cicr r/w 00000000 000042 h timer mode control register tmcr r/w! 001C0000 000043 h compare/data select register coer r/w CCCC0000 000044 h compare buffer mode control register cmcr r/w CCCC0000 000045 h zero detect output control register zoctr w CCCx0000 000046 h output control buffer register octbr r/w 11111111 000047 h zero detect interrupt control register zicr r/w! 0 C C C x x x x 000048 h output compare buffer register 0 ocpbr0 w xxxxxxxx 000049 h C Cxxxxxx 00004a h output compare buffer register 1 ocpbr1 w xxxxxxxx 00004b h C Cxxxxxx 00004c h output compare buffer register 2 ocpbr2 w xxxxxxxx 00004d h C Cxxxxxx
23 MB90660A series (continued) (continued) address register name access *2 resource name initial value 00004e h output compare buffer register 3 ocpbr3 w multi-function timer xxxxxxxx 00004f h C Cxxxxxx 000050 h compare clear buffer register clrbr w 00000000 000051 h CC000000 000052 h dead time control register dtcr r/w! 00000000 000053 h dead time setting register dtsr w x x x 0 x x x x 000054 h dead time compare register dtcmr w xxxxxxxx 000055 h vacancy *1 000056 h timer pin control register tpcr r/w 16-bit reload timer C001C000 000057 h C011C010 000058 h to 5e h vacancy *1 00005f h machine clock division control register cdcr w uart C C CC1111 000060 h to 8f h vacancy *1 000090 h to 9e h system reserved area *1 00009f h delayed interrupt source generate/ cancel register dirr r/w delayed interrupt generator module CCCCCCC0 0000a0 h low power mode control register lpmcr r/w! low power 00011000 0000a1 h clock select register ckscr r/w! 11111100 0000a2 h to a7 h system reserved area *1 0000a8 h watchdog timer control register wdtc r/w! watchdog timer x C x x x 1 1 1 0000a9 h timebase timer control register tbtc r/w! timebased timer 1CC00100 0000aa h to af h system reserved area *1 0000b0 h interrupt control register 00 icr00 r/w! interrupt controller 00000111 0000b1 h interrupt control register 01 icr01 r/w! 00000111 0000b2 h interrupt control register 02 icr02 r/w! 00000111 0000b3 h interrupt control register 03 icr03 r/w! 00000111 0000b4 h interrupt control register 04 icr04 r/w! 00000111 0000b5 h interrupt control register 05 icr05 r/w! 00000111 0000b6 h interrupt control register 06 icr06 r/w! 00000111 0000b7 h interrupt control register 07 icr07 r/w! 00000111
24 MB90660A series (continued) *1: access prohibited *2: registers marked r/w! in the access column include some bits that can only be read or only be written. for details, see the register list for each resource. * : when a register marked r/w!, r/w* or w in the access column is accessed by a read-modify-write instruction (such as a bit set instruction), the bit operated on by the instruction will be set to the specified value, but a malfunction will occur if there are any other bits which can only be written. therefore, do not access these locations using these instructions. description of initial values 0: the initial value of this bit is 0. 1: the initial value of this bit is 1. *: the initial value of this bit is 1 or 0. (this is determined depending on the level of the md0 to md2 pins.) x: the initial value of this bit is undefined. C: this bit is not used. the initial value is undefined. note: the initial value results for bits which can only be written when initialized by a reset. note that this is not the value when read. also, sometimes lpmcr, ckscr and wdtc are initialized and sometimes they are not depending on the type of reset. if they are initialized, the initial value is used. address register name access *2 resource name initial value 0000b8 h interrupt control register 08 icr08 r/w! interrupt controller 00000111 0000b9 h interrupt control register 09 icr09 r/w! 00000111 0000ba h interrupt control register 10 icr10 r/w! 00000111 0000bb h interrupt control register 11 icr11 r/w! 00000111 0000bc h interrupt control register 12 icr12 r/w! 00000111 0000bd h interrupt control register 13 icr13 r/w! 00000111 0000be h interrupt control register 14 icr14 r/w! 00000111 0000bf h interrupt control register 15 icr15 r/w! 00000111 0000c0 h to ff h system reserved area *1
25 MB90660A series n interrupt sources, interrupt vectors and interrupt control registers : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (no stop request). : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (with stop request). : indicates that the interrupt request flag is not cleared by the i 2 os interrupt clear signal. note: do not specify i 2 os activation in interrupt control registers that do not support i 2 os. interrupt source i 2 os support interrupt vector interrupt control register number address icr address reset #08 08 h ffffdc h int9 instruction #09 09 h ffffd8 h exception #10 0a h ffffd4 h multi-function timer dtti input #12 0c h ffffcc h icr00 0000b0 h external interrupt #0 #13 0d h ffffc8 h icr01 0000b1 h external interrupt #4 #14 0e h ffffc4 h multi-function timer trigger input or zero detect #15 0f h ffffc0 h icr02 0000b2 h multi-function timer zero detect #17 11 h ffffb8 h icr03 0000b3 h multi-function timer overflow, compare clear or zero detect #19 13 h ffffb0 h icr04 0000b4 h external interrupt #1 #21 15 h ffffa8 h icr05 0000b5 h multi-function timer compare match #22 16 h ffffa4 h external interrupt #5 #23 17 h ffffa0 h icr06 0000b6 h pwm underflow #24 18 h ffff9c h external interrupt #2 #25 19 h ffff98 h icr07 0000b7 h external interrupt #6 #26 1a h ffff94 h 16-bit reload timer #0 #27 1b h ffff90 h icr08 0000b8 h 16-bit reload timer #1 #28 1c h ffff8c h 16-bit reload timer #2 #29 1d h ffff88 h icr09 0000b9 h 16-bit reload timer #3 #30 1e h ffff84 h end of a/d converter conversion #31 1f h ffff80 h icr10 0000ba h timebase timer interval interrupt #34 22 h ffff74 h icr11 0000bb h uart send complete #35 23 h ffff70 h icr12 0000bc h uart receive complete #37 25 h ffff68 h icr13 0000bd h external interrupt #3 #39 27 h ffff60 h icr14 0000be h external interrupt #7 #40 28 h ffff5c h delayed interrupt generator module #42 2a h ffff54 h icr15 0000bf h
26 MB90660A series n peripheral resources 1. parallel port the MB90660A includes 39 i/o pins, 4 input pins, and 8 open-drain output pins. port 0, 1, 2, 3 and 6 are i/o ports. they are used for input when the corresponding direction register value is 0, and for output when the value is 1. port 5 is an open-drain port. it is used as a port when the analog input enable register is 0. ports 40 to 43 are i/o ports. they are used for input when the corresponding direction register value is 0, and for output when the value is 1. ports 44 to 47 are input ports which can only be used for reading data. (1) register configuration notes: there are no register bits for bits 15 to 12 of port 3. there is no register bit for bit 7 of port 6. bits 7 to 4 of port 4 can only be used to read data. bit read/write initial value bit pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdr1, 3 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 15 14 13 12 11 10 9 8 pd 7pd 6pd 5pd 4pd 3pd 2pd 1pd 0 pdr0, 2, 6 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 read/write initial value bit read/write initial value bit read/write initial value pd57 pd56 pd55 pd54 pd53 pd52 pd51 pd50 pdr5 (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) 15 14 13 12 11 10 9 8 pd47 pd46 pd45 pd44 pd43 pd42 pd41 pd40 pdr4 (r) (x) (r) (x) (r) (x) (r) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 port data register address : pdr1 000001 h : pdr3 000003 h port data register address : pdr0 000000 h : pdr2 000002 h : pdr6 000006 h (pdbr) port data register address : 000005 h port data register address : 000004 h
27 MB90660A series notes: there are no register bits for bits 15 to 12 of port 3. there are not register bits for bits 7 to 4 of port 4 there is no ddr for port 5. there is no register bit for bit 7 of port 6. bit read/write initial value bit dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddr1, 3 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 dd 7dd 6dd 5dd 4dd 3dd 2dd 1dd 0 ddr0, 2, 4, 6 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 read/write initial value port direction register address : ddr1 000011 h : ddr3 000013 h port direction register address : ddr0 000010 h : ddr2 000012 h : ddr4 000014 h : ddr6 000016 h bit read/write initial value ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 ader (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) 15 14 13 12 11 10 9 8 analog input enable register address : 000015 h
28 MB90660A series (2) block diagrams data register direction register data register read data register write direction register write direction register read pin internal data bus data register ader data register read data register write ader register write ader register read pin rmw (read-modify- write instruction) internal data bus internal data bus data register read pin ? i/o ports ? open-drain ports (also used for analog input) ? input ports
29 MB90660A series 2. multi-function timer the multi-function timer controls up to 7 realtime output pins, and includes the following functions. ? interval timer function it can output pulses or generate an interrupt at a fixed interval. ? pwm output function can perform output for a fixed cycle pulse while changing the duty ratio (ratio between l output width and h output width) in realtime. ? 3-phase ac sine wave output (inverter control output) function can perform 3-phase ac sine wave output using ac motor inverter control, etc. (using any setting for the non- overlap interval) this timer also has the following characteristics. ? pulse cycle control using 14-bit timer a machine cycle of 1, 2, 8 or 16 can be selected based on pre-scalars as the clock source (minimum resolution of 62.5 ns at 16 mhz operation). can use a carrier frequency up to 30 khz at 8-bit stop when used for ac motor control. up count only or up/down count can be selected using the count mode selection. possessing a buffer, cycle can be changed in realtime by transferring data from buffer upon zero detect. ? duty control using compare registers possessing four compare registers, output pulse duty can be set for four separate channels. each possessing a separate buffer, duty can be changed in realtime by transferring data from buffer upon zero detect or comparison. ? non-overlap control using dead time timer dead time timer can be used to generate pwm output for three channels or even reversed signals with non- overlap, thus allowing an ac motor control wave (u, v, w, x, y, z) to be generated. a machine cycle of 1, 4, 8 or 32 can be selected based on pre-scalars as the clock source for the dead timer (minimum resolution of 62.5 ns at 16 mhz operation) ? forced stop control using dtti pin input the forced pin output level can be fixed by dtti pin input or software. inactive control can be performed during ac motor control using dtti pin input. external pin control even during vibration stop can be performed through clockless dtti pin input. ? event detection and interrupt generation using various flags flags can be set and/or interrupts generated upon zero detect, overflow, detect of match with compare registers, or clear by trg pin input, or any match of the compare registers for the four channels for the 14-bit timer (also possible to disable interrupt output).
30 MB90660A series (1) register configuration clrr address address address address address : 000040 h : 000041 h : 000042 h : 000043 h : 000044 h address : 000045 h address : 000046 h address : 000047 h address : 000006 h address address address : 000052 h : 000053 h : 000054 h address : 000048h to : 00004fh address (r/w) (r/w) (r/w) (r/w) (r/w) (w) (r/w) (r/w) (w) (r/w) (w) (w) (w) (w) (w) timer control status register compare interrupt control register timer mode control register compare/data select register compare buffer mode control register zero detect output control register output control register output control buffer register zero detect interrupt control register port data buffer register dead time timer control register dead time setting register dead time compare register output compare buffer registers 0 to 3 output compare registers 0 to 3 compare clear buffer register compare clear register : 000050 h : 000051 h tcsr cicr tmcr coer cmcr dtcr dtsr dtcmr pdbr zoctr octr octbr zicr ocpr0 to 3 ocpbr0 to 3 clrbr 14 bits 8 bits 14 bits
31 MB90660A series (2) block diagrams ? timer/wave generator block diagram 14-bit timer stcr, tmst, mode ces1, 0 tcs1, 0 pre-scalar (1, 2, 8 or 16 machine cycles) count clock comparator clrr, clrbr zero detect zero detect interrupt mask zosc, ime, cyc3 to 0 trg (external input) interrupt control iios tcie, tcir tzie, tzir tmie, tmir cie3 to 0, cir3 to 0 rt0 (external output) zero detect pin control zsb0 comparator, pin control ro01, 0 pdr6 pd66 ocpr0, ocpbr0 rt1 (to output selector) zero detect pin control zsb1 comparator, pin control ro11, 0 pdr6 pd60 ocpr1, ocpbr1 rt2 (to output selector) zero detect pin control zsb2 comparator, pin control ro21, 0 pdr6 pd61 ocpr2, ocpbr2 rt3 (to output selector) zero detect pin control zsb3 comparator, pin control ro31, 0 pdr6 pd62 ocpr3, ocpbr3 set, reset set, reset, transfer zero detect set, reset set, reset, transfer set, reset set, reset, transfer set, reset set, reset, transfer buffer transfer control tren, tmsk, bfs1, 0 transfer request reverse or clear timer clear zero detect interrupt timer interrupt compare interrupt 14
32 MB90660A series ? output selector/dead time generator block diagram mode select dtti interrupt dtie, dtif dtti (external input) p60/rt1/u p63/x (external output) dtti control toce, toc1, 0 nrsl comparator 8-bit timer pre-scalar dead time wave generator dead time wave generator dead time wave generator compare selector comparator 8-bit timer pre-scalar comparator 8-bit timer pre-scalar selector wave control dmod, dt1, 0 dcs1, 0 selector p61/rt2/v p64/y (external output) active level u x v y w z active level mode select active level mode select inactive inactive division select count clock division select count clock division select count clock dtcmr 8 rt3 (from wave generator) rt2 (from wave generator) rt1 (from wave generator) flag set dtti interrupt inactive p62/rt3/w p65/z (external output) compare compare
33 MB90660A series 3. uart the uart is a serial i/o port for asynchronous (start/stop) or clk synchronous communications with external resources. it has the following characteristics: ? full duplex double buffering ? asynchronous (start/stop) or clk synchronous communications ? multiprocessor mode support ? internal dedicated baud-rate generator asynchronous : 19230/9615/31250/4808/2404/1202 bps clk synchronous : 2 m/1 m/500 k/250 k bps ? free baud-rate setting based on external clock ? error detection functions (parity, framing and overrun) ? use of nrz coded transfer signal ? supports intelligent i/o services (1) register configuration bit md1 md0 cs2 cs1 cs0 scke soe serial mode register (smr) 76543210 address : 000024 h bit pen p sbl cl a/d rec rxe txe serial control register (scr) 15 14 13 12 11 10 9 8 address : 000025 h bit d7 d6 d5 d4 d3 d2 d1 d0 serial input register serial output register (sidr/sodr) 76543210 address : 000026 h bit pe ore fre rdrf tdre rie tie serial status register (ssr) 15 14 13 12 11 10 9 8 address : 000027 h bit div3div2div1div0 machine clock division control register (cdcr) 15 14 13 12 11 10 9 8 address : 00005f h scr 15 8 7 0 cdcr ssr smr sidr (r)/sodr (w) (r/w) (r/w) (w) 8 bits 8 bits
34 MB90660A series (2) block diagram control signal dedicated baud rate generator 16-bit timer0 (connected internally) external clock sin clock selector receive interrupt (to cpu) send interrupt (to cpu) sck receive controller start bit detect circuit receive bit counter receive parity counter send controller send start circuit send bit counter send parity counter receive status determination circuit receive shifter receive end send shifter send start receive error generator signal for ei 2 os (to cpu) sidr sodr f 2 mc-16 bus smr register md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie scr register ssr register transfer clock receive clock sot control signal
35 MB90660A series 4. 10-bit, 8-channel a/d converter (with 8-bit resolution mode) this 10-bit, 8-channel a/d converter is used to convert analog input voltage to corresponding digital values. it has the following features. ? conversion time: 6.13 m s per channel (includes sample and hold time at 98 machine cycles/machine clock of 16 mhz) ? sample hold time: 3.75 m s per channel (60 machine cycles per machine clock of 16 mhz) ? rc-type sequential approximation conversion with sample and hold circuits ? 10-bit or 8-bit resolution ? analog input can be selected from 8 channels single conversion mode : one channel selected for conversion scan conversion mode : consecutive multiple channels converted (programmable with max. eight channels) repetitive conversion mode : data on the specified channel is converted repeatedly stop conversion mode : once one channel is converted, operations stop and the device waits until started again (conversion start can be synchronized) ? at the end of each a/d conversion, an interrupt request to the cpu can be generated. this interrupt can be used to activate i 2 os or transfer a/d conversion results to memory, making it useful when continuous processing is desired. ? conversion can be triggered by software, an external trigger (falling edge), and/or a timer (rising edge). (1) register configuration bit read/write initial value busy int inte paus sts1 sts0 strt reserved adcs (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (w) (0) (? (0) 15 14 13 12 11 10 9 8 a/dcontrol status register (upper) address : 00002d h bit read/write initial value md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 adcs (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 a/d control status register (lower) address : 00002c h bit read/write initial value s10d9d8 adcr (r/w) (0) (r) (0) (r) (0) (r) (0) (r) (0) (r) (0) (r) (x) (r) (x) 15 14 13 12 11 10 9 8 a/d data register (upper) address : 00002f h bit read/write initial value d7 d6 d5 d4 d3 d2 d1 d0 adcr (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) 76543210 a/d data register (lower) address : 00002e h
36 MB90660A series (2) block diagram avr av ss an0 an1 an2 an3 an4 an5 an6 an7 mpx sample and hold circuits comparator d/a converter sequential comparison register data register a/d control register 1 a/d control register 2 adcr0, 1 adcs0, 1 atg multi-function timer (rt0 output) timer start trigger start operation clock pre-scalar av cc peripheral clock input circuit decoder data bus
37 MB90660A series 5. pwm timer this block, which is an 8-bit reload timer module, outputs the pulse width modulation (pwm) using pulse output control corresponding to the timer operation. in terms of hardware, this block possesses an 8-bit down counter, two 8-bit reload registers for setting l width and h width, a control register, external pulse output pin, and interrupt output circuit to achieve the following functions. ? pwm output operation : pulse waves of any period and duty factor are output. this block can also be used as a d/a converter with an external circuit. interrupt requests can be output based on counter underflow. (1) register configuration (2) block diagram pwm reload register 8 bits pwm operation mode control register address: 000020 h 000022 h 000023 h pwmc prll prlh (r/w) (r/w) (r/w) operation mode control hold ??pulse width reload value hold ??pulse width reload value (functions) irq tbt output main clock divided by 512 tbt output main clock divided by 4 count clock selection pwmo output latch pcnt (down counter) reload l/h selector prll prlh prlbh clear reverse pen operation mode control pwmc pwm output enabled (port) l/h select f 2 mc-16 bus tbt: timebase timer
38 MB90660A series 6. 16-bit reload timer (with event count function) the 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, control register, and 4 timer pins (i/o set by timer pin select register). three internal clocks and an external clock can be selected as input clocks. a toggle output waveform is output at the output pin (tot) in reload mode, while a square wave indicating that the timer is counting is output at the output pin in single-shot mode. the input pin (tin) can be used for event input in even count mode, and for trigger input or gate input in internal clock mode. this product has this timer built into four channels. (1) register configuration read/write initial value (? (? (? (? (? (? (? (? (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) bit 15 14 13 12 11 10 9 8 csl1csl0 mod2 mod1 bit 76543210 mod0 reserved outl reld inte uf cnte trg tmcsr 0 to 3 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value bit read/write initial value ote3 csb3 csa3 ote2 csb2 csa2 (? (? (r/w) (0) (r/w) (1) (r/w) (1) (? (? (r/w) (0) (r/w) (1) (r/w) (0) 15 14 13 12 11 10 9 8 control status register (upper) address : channel 0 000031 h : channel 1 000035 h : channels 2 000039 h : channels 3 00003d h control status register (lower) address : channel 0 000030 h : channel 1 000034 h : channels 2 000038 h : channels 3 00003c h bit 15 14 13 12 11 10 9 8 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) read/write initial value 16-bit timer register (upper) 16-bit reload register (upper) address : channel 0 000033 h : channel 1 000037 h : channels 2 00003b h : channels 3 00003f h timer pin control register (upper) address : 000057 h bit read/write initial value ote1 csb1 csa1 ote0 csb0 csa0 tpcr (? (? (r/w) (0) (r/w) (0) (r/w) (1) (? (? (r/w) (0) (r/w) (0) (r/w) (0) 76543210 timer pin control register (lower) address : 000056 h bit 76543210 tmr/ tmrlr 0 to 3 (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) read/write initial value 16-bit timer register (lower) 16-bit reload register (lower) address : channel 0 000032 h : channel 1 000036 h : channels 2 00003a h : channels 3 00003e h
39 MB90660A series (2) block diagram 16-bit reload register 16-bit down counter clock selector reload reld outl inte uf cnte trg out ctl csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl 3 peripheral clock prescaler clear exck gate irq tin tot uf serial baud rate (channel 0 only) clear i 2 osclr 16-bit reload timer channel 0 tin0 tot0 16-bit reload timer channel 1 tin1 tot1 16-bit reload timer channel 2 tin2 tot2 16-bit reload timer channel 3 tin3 tot3 tim0 tim1 tim2 tim3 i/o pins for timer* * : timer channel and direction (i/o) can be selected for each pin. f 2 mc-16 bus selector f 2 1 f 2 3 f 2 5 trigger
40 MB90660A series 7. external interrupts in addition to h and l, rising and falling edge can be selected as the external interrupt level for a total of four interrupt level types. (1) register configuration (2) block diagram bit read/write initial value en7 en6 en5 en4 en3 en2 en1 en0 enir (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 interrupt enable register address : 000028 h bit read/write initial value er7 er6 er5 er4 er3 er2 er1 er0 eirr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 interrupt source register address : 000029 h bit read/write initial value lb7 la7 lb6 la6 lb5 la5 lb4 la4 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 request level setting register (upper) address : 00002b h bit read/write initial value request level setting register (lower) address : 00002a h lb3 la3 lb2 la2 lb1 la1 lb0 la0 elvr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 8 8 8 16 8 interrupt enable register interrupt source register request level setting register gate source f/f edge detector request input irq f 2 mc-16 bus
41 MB90660A series 8. delayed interrupt generation module the delayed interrupt generation module is used to generate an interrupt for task switching. if this module is used, an interrupt request to the f 2 mc-16l cpu can be generated or cancelled by software. (1) register configuration the dirr register controls the generation and cancellation of delayed interrupt requests. a delayed interrupt request is generated when 1 is written to this register, while a delayed interrupt request is cancelled when 0 is written here. request cancel status results upon reset. although either 0 or 1 may be written into reserved bits, we recommend using the set bit and clear bit instructions when accessing this register in consideration of possible future extensions. (2) block diagram bit read/write initial value r0dirr (? (? (? (? (? (? (? (? (? (? (? (? (? (? (r/w) (0) 15 14 13 12 11 10 9 8 delayed interrupt request generation/cancel register address : 000009 h delayed interrupt source generation/ cancel decoder source latch f 2 mc-16 bus
42 MB90660A series 9. watchdog timer and timebase timer functions the watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit timebase timer as the clock source, a control register, and a watchdog reset controller. in addition to an 18-bit timer, the timebase timer consists of a circuit for controlling interval interrupts. note that the timebase timer uses the main clock regardless of the status of the mcs bit within the ckscr register. (1) register configuration (2) block diagram bit read/write initial value ponr wrst erst srst wte wt1 wt0 wdtc (r) (x) (? (? (r) (x) (r) (x) (r) (x) (w) (1) (w) (1) (w) (1) 76543210 watchdog timer control register address : 0000a8 h bit read/write initial value reserved tbie tbof tbr tbc1 tbc0 tbtc (? (1) (? (? (? (? (r/w) (0) (r/w) (0) (w) (1) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 timebase timer control register address : 0000a9 h tbtc ponr wrst erst srst tbc0 tbr tbie tbof tbc1 wt1 wt0 wte wdtc selector selector and 2-bit counter clr of clr watchdog reset generator to wdgrst internal reset generator from power-on generator rst pin from rst bit of stbyc register timebase interrupt clock input 2 12 2 14 2 16 2 19 tbtres timebase timer 2 12 2 14 2 16 2 19 main clock (osc oscillation) qr s 2 2 2 9 to pwm timer f 2 mc-16 bus
43 MB90660A series 10. low power consumption controller (cpu intermittent operation function, stable oscillation wait time, and clock multiplier function) the following operation modes are available: pll clock mode, pll sleep mode, clock mode, main clock mode, main sleep mode and stop mode. operation modes other than pll clock mode are classified as low power consumption modes. main clock mode and main sleep mode are modes where the microcontroller operates using the main clock (osc oscillation clock) only. in these modes, the main clock divided by two is used as the operation clock and the pll clock (vco oscillation clock) is stopped. in pll sleep mode and main sleep mode, only the operation clock of the cpu is stopped, while operations besides the cpu clock continue. in clock mode, only the timebase timer is allowed to operate. in stop mode, oscillation is stopped, allowing data to be held at the lowest power consumption possible. the cpu intermittent operation function causes the clock provided to the cpu to function intermittently when accessing registers, internal memory, internal resources and the external bus. this allows processing to be performed at lower power consumption by reducing the cpu execution speed while continuing to provide a high speed clock to internal resources. the pll clock multiplier can be selected as 1, 2, 3 or 4 using the cs1 and cs0 bits. the stable oscillation wait time for the main clock when stop mode is cancelled can be set using the ws1 and ws0 bits. (1) register configuration bit read/write initial value stp slp spl rst reserved cg1 cg0 reserved lpmcr (w) (0) (w) (0) (r/w) (0) (w) (1) (? (1) (r/w) (0) (r/w) (0) (? (0) 76543210 low power consumption mode control register address : 0000a0 h bit read/write initial value reserved mcm ws1 ws0 reserved mcs cs1 cs0 ckscr (? (1) (r) (1) (r/w) (1) (r/w) (1) (? (1) (r/w) (1) (r/w) (0) (r/w) (0) 15 14 13 12 11 10 9 8 clock selection register address : 0000a1 h
44 MB90660A series (2) block diagram ckscr mcm mcs ckscr cs1 cs0 ckscr ws0 lpmcr spl pin high-impedance controller ws1 pll multiplier circuit clock generator for cpu cpu cpu clock selector clock input 2 4 2 13 2 15 2 18 timebase timer 2 12 2 14 2 16 2 19 lpmcr cg1 cg0 cpu intermittent operation function cycle count selector lpmcr rst lpmcr slp stp standby controller rst cancel clock generator for peripheral resources 1234 2 1 cpu clock peripheral resource clock main clock (osc oscillation) 0, 9, 17 or 33 intermittent cycle select stable oscillation wait time selector interrupt request or rst pin hi-z to watchdog timer wdgrst rst pin internal rst internal reset generator 2 2 2 9 to pwm timer f 2 mc-16 bus
45 MB90660A series 11. interrupt controller the interrupt control register is located within the interrupt controller. its status conforms to all i/o possessed by the interrupt function. this register includes the following three functions. ? sets the interrupt level of the corresponding peripheral resource ? selects whether to use conventional interrupts or extended intelligent i/o services for the interrupt of the corresponding peripheral resource ? selects the channel for the extended intelligent i/o services (1) register configuration note: since read-modify-write type instructions can cause a malfunction, do not access using these instructions. read/write initial value (w) (0) (w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (1) (r/w) (1) (r/w) (1) bit 15 14 13 12 11 10 9 8 bit76543210 ics3 ics1 ics2 s1 ics0 or s0 or ise il2 il1 il0 icr01, 03, 05, 07, 09, 11, 13, 15 ics3 ics1 ics2 s1 ics0 or s0 or ise il2 il1 il0 icr00, 02, 04, 06, 08, 10, 12, 14 (w) (0) (w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (1) (r/w) (1) (r/w) (1) read/write initial value interrupt control register address : icr01 0000b1 h : icr03 0000b3 h : icr05 0000b5 h : icr07 0000b7 h : icr09 0000b9 h : icr11 0000bb h : icr13 0000bd h : icr15 0000bf h interrupt control register address : icr00 0000b0 h : icr02 0000b2 h : icr04 0000b4 h : icr06 0000b6 h : icr08 0000b8 h : icr10 0000ba h : icr12 0000bc h : icr14 0000be h
46 MB90660A series (2) block diagram ise interrupt request/ i 2 os request (peripheral resource) (cpu) interrupt level determines interrupt/i 2 os priority level il2 il1 il0 32 4 4 3 4 i 2 os select ics3 i 2 os vector (cpu) selects i 2 os vector ics2 ics1 ics0 4 4 4 s1 i 2 os end condition detects i 2 os end condition s0 2 2 2 f 2 mc-16 bus
47 MB90660A series n electrical characteristics 1. absolute maximum rating (v ss = av ss = 0.0 v) *1: av cc and v avr must not exceed v cc . *2: v i and v o must not exceed v cc + 0.3 v. *3: maximum output current specifies the peak value of one corresponding pin. *4: average output current specifies the average current within a 100 ms interval flowing through one corresponding pin. *5: average total output current specifies the average current within a 100 ms interval flowing through all corresponding pins. *6: md2 pin of mb90p663a *7: pins excluding p60/rt1/u, p61/rt2/v, p62/rt3/w, p63/x, p64/y and p65/z pins *8: p60/rt1/u, p61/rt2/v, p62/rt3/w, p63/x, p64/y and p65/z pins warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc * 1 v ss C 0.3 v ss + 7.0 v v avr * 1 v ss C 0.3 v ss + 7.0 v programming voltage v pp v ss C 0.3 13.0 v *6 input voltage* 2 v i v ss C 0.3 v cc + 0.3 v output voltage* 2 v o v ss C 0.3 v cc + 0.3 v l level maximum current* 3 i ol1 10 ma *7 i ol2 30 ma *8 l level average output current* 4 i olav1 4ma*7 i olav2 20 ma *8 l level total average output current* 5 2i olav1 30 ma *7 2i olav2 60 ma *8 h level maximum output current* 3 i oh C10 ma h level average output current* 4 i ohav C4 ma h level total average output current* 5 2i ohav C40 ma power consumption pd 400 mw operating temperature t a C40 +85 c storage temperature t stg C55 +150 c
48 MB90660A series 2. recommended operating conditions (v ss = av ss = 0.0 v) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol ratings unit remarks min. max. power supply voltage v cc 2.7 5.5 v during normal operation v cc 2.0 5.5 stop operation status is held operating temperature t a C40 +85 c
49 MB90660A series 3. dc characteristics (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) * : applies to pins p40 to p47, p50 to p57, p60 to p66, dtti and rst . parameter symbol pin name conditions value unit remarks min. typ. max. h level output voltage v oh except p50 to p57 v cc = 4.5 v i oh = C4.0 ma v cc C 0.5 v v cc = 2.7 v i oh = C1.6 ma v cc C 0.3 v l level output voltage v ol1 except p60 to p65 v cc = 4.5 v i ol = 4.0 ma 0.4 v v cc = 2.7 v i ol = 2.0 ma 0.4 v v ol2 p60 to p65 v cc = 4.5 v i ol = 15.0 ma 1.0 v v cc = 2.7 v i ol = 2.0 ma 0.4 v h level input voltage v ih pins except v ihs , v ihm 0.7 v cc vcc + 0.3 v v ihs hysteresis input pins 0.8 v cc vcc + 0.3 v* v ihm md pin vcc C 0.3 vcc + 0.3 v l level input voltage v il pins except v ils , v ilm vss C 0.3 0.3 v cc v v ils hysteresis input pins vss C 0.3 0.2 v cc v* v ilm md pin vss C 0.3 vss + 0.3 v input leakage current i il except p50 to p57 v cc = 5.5 v v ss < v i < v cc C10 10 m a pull-up resistor r pup pins for which pull-up option is selected when v cc = 5.0 v 25 100 k w when v cc = 3.0 v 40 200 k w pull-down resister r pdn pins for which pull-down options selected when v cc = 5.0 v 25 80 200 k w when v cc = 3.0 v 40 160 400 k w supply current i cc when v cc = 5.0 v internal 16 mhz operation 50 70 ma during normal operation i ccs internal 16 mhz operation 25 30 ma during sleep i cc when v cc = 3.0 v internal 8 mhz operation 10 20 ma during normal operation i ccs internal 8 mhz operation 5 10 ma during sleep i cch t a = 25c 0.1 10 m a during stop input capacitance c in except av cc , av ss , v cc and v ss 10 pf open-drain output leakage current i leak p50 to p57 0.1 10 m a n channel tr off
50 MB90660A series 4. ac characteristics (1) clock timing values ?used at v cc = 5.0 v 10% (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) * : the frequency fluctuation ratio represents the maximum fluctuation from the central frequency as a percentage when a multiplier is locked. ?used at v cc = 2.7 v (minimum) (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter symbol pin name conditions value unit remarks min. max. oscillation frequency f c x0, x1 332mhz oscillation cycle time t c x0, x1 31.25 333 ns frequency fluctuation ratio* (when locked) yf 3% input clock pulse width p wh p wl x0 10 ns use duty ratio of 30% to 70% as guideline input clock rising and falling times t cr t cf x0 5ns internal operating clock frequency f cp 1.5 16 mhz internal operating clock cycle time t cp 62.5 666 ns parameter symbol pin name conditions value unit remarks min. max. oscillation frequency f c x0, x1 316mhz oscillation cycle time t c x0, x1 62.5 333 ns input clock pulse width p wh p wl x0 20 ns use duty ratio of 30% to 70% as guideline input clock rising and falling times t cr t cf x0 5ns internal operating clock frequency f cp 1.5 8 mhz internal operating clock cycle time t cp 125 666 ns + central frequency + a a f 0 ? f = a f 0 100 (%)
51 MB90660A series (2) recommended resonator manufacturers x0 x1 c1 c2 *2 *1 r far *1 *1: fujitsu acoustic resonator ? sample application of piezoelectric resonator (far family) inquiry: fujitsu limited far part number (built-in capacitor type) fre- quency (mhz) dumping resistor initial deviation of far frequency (t a = +25 c) temperature characteristics of far frequency (t a = C20 c to +60 c) loading* 2 capacitors far-c4cc-02000-l20 2.00 510 w 0.5% 0.5% built-in far-c4sa-04000-m01 4.00 0.5% 0.5% far-c4cb-04000-m00 0.5% 0.5% far-c4cb-08000-m02 8.00 0.5% 0.5% far-c4cb-12000-m02 12.00 0.5% 0.5% far-c4cb-16000-m02 16.00 0.5% 0.5% far-c4cb-20000-l14b 19.80 0.5% 0.5% far-c4cb-24000-l14a 23.76 0.5% 0.5%
52 MB90660A series ? sample application of ceramic resonator ? mask products (continued) resonator manufacturer* resonator frequency (mhz) c1 (pf) c2 (pf) r kyocera corporation kbr-2.0ms 2.00 150 150 pbrc2.00a 150 150 kbr-4.0msa 4.00 33 33 680 w kbr-4.0mks built-in built-in 680 w pbrc4.00a 33 33 680 w pbrc4.00b built-in built-in 680 w kbr-6.0msa 6.00 33 33 kbr-6.0mks built-in built-in pbrc6.00a 33 33 pbrc6.00b built-in built-in kbr-8.0m 8.00 33 33 560 w pbrc8.00a 8.00 33 33 pbrc8.00b built-in built-in kbr-10.0m 10.00 33 33 330 w pbrc10.00b built-in built-in 680 w kbr-12.0m 12.00 33 33 330 w pbrc12.00b built-in built-in 680 w x0 x1 c1 c2 r *
53 MB90660A series (continued) inquiry: kyocera corporation avx corporation north american sales headquarters: tel 1-803-448-9411 avx limited european sales headquarters: tel 44-1252-770000 avx/kyocera h.k. ltd. asian sales headquarters: tel 852-363-3303 murata mfg. co., ltd. murata electronics north america, inc.: tel 1-404-436-1300 murata europe management gmbh: tel 49-911-66870 murata electronics singapore (pte.) ltd.: tel 65-758-4233 resonator manufacturer* resonator frequency (mhz) c1 (pf) c2 (pf) r murata mfg. co., ltd. csa2.00mg040 2.00 100 100 cst2.00mg040 built-in built-in csa4.00mg040 4.00 100 100 cst4.00mgw040 built-in built-in csa6.00mg 6.00 30 30 cst6.00mgw built-in built-in csa8.00mtz 8.00 30 30 cst8.00mtw built-in built-in csa10.00mtz 10.00 30 30 cst10.00mtw built-in built-in csa12.00mtz 12.00 30 30 cst12.00mtw built-in built-in csa16.00mxz040 16.00 15 15 cst16.00mxw0c3 built-in built-in csa20.00mxz040 20.00 10 10 csa24.00mxz040 24.00 5 5 csa32.00mxz040 32.00 5 5
54 MB90660A series ac specification values are specified for the measured reference voltages given below. 0.8 v cc 0.2 v cc t cf t cr t c p wl p wh 5.5 4.5 3.3 2.7 0 1.5 3 8 16 f cp (mhz) normal operating range note: even in the case of evaluation tool, operation is assured down to 2.7 v. 12 16 8 9 4 03 48 16 24 32 f c (mhz) pll operation warranty range relationship between clock frequency and supply voltage multiplied by 4 multiplied by 3 multiplied by 2 multiplied by 1 no multiplication internal clock oscillation clock relationship between oscillator frequency and internal operating clock frequency power supply v cc (v) internal clock f cp (mhz) ? clock timing ? pll operation warranty range 0.8 v cc 0.2 v cc hysteresis input pin pins except hysteresis input and md input 0.7 v cc 0.3 v cc 2.4 v 0.8 v output pin ? input signal waveforms ? output signal waveforms
55 MB90660A series (3) reset input specifications (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) (4) power-on reset (v ss = 0.0 v, t a = C40c to +85c) * : v cc should be lower than 0.2 v before power supply rise. notes: ? the above specifications are the numeric values needed for causing a power-on reset. ? there are built in resisters initialized only by power on reset in the device. turn on power supply according to the specification at the point of this initialization. parameter symbol pin name conditions value unit remarks min. max. reset input time t rstl rst 16 machine cycle parameter symbol pin name conditions value unit remarks min. max. power supply rise time t r v cc 30 ms * power supply cutoff time t off v cc 1 ms due to repeated operations rst 0.2 v cc 0.2 v cc t rstl ram data maintained 2.7 v t r 0.2 v v cc 5.0 v 2.0 v v ss v cc a rise time of 50 mv/ms or less is recommended. an abrupt change in the supply voltage may activate power-on reset. if the supply voltage must be changed during operation, the voltage change should be smooth without sudden fluctuations.
56 MB90660A series (5) uart timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) notes: ? these are ac specification during clk synchronous mode. ?c l is the load capacity value assigned to the pin during testing. ?t cp is the machine cycle time (unit: ns). parameter symbol pin name conditions value unit remarks min. max. serial clock cycle time t scyc sck 8 t cp ns c l = 80 pf + 1 ttl for internal clock operation output pin sck ? sot delay time t slov sck sot v cc = 5.0 v 10% C80 80 ns v cc = 3.0 v 10% C120 120 ns valid sin ? sck - t ivsh sck sin v cc = 5.0 v 10% 100 ns v cc = 3.0 v 10% 200 ns sck - ? valid sin hold time t shix sck sin v cc = 5.0 v 10% 60 ns v cc = 3.0 v 10% 120 ns serial clock h pulse width t shsl sck 4 t cp ns c l = 80 pf + 1 ttl for external clock operation output pin serial clock l pulse width t slsh sck 4 t cp ns sck ? sot delay time t slov sck sot v cc = 5.0 v 10% 150 ns v cc = 3.0 v 10% 200 ns valid sin ? sck - t ivsh sck sin v cc = 5.0 v 10% 60 ns v cc = 3.0 v 10% 120 ns sck - ? valid sin hold time t shix sck sin v cc = 5.0 v 10% 60 ns v cc = 3.0 v 10% 120 ns
57 MB90660A series sck sot sin 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v 2.4 v t scyc t slov t ivsh t shix sck sot sin 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shsl t slsh t slov t ivsh t shix ? internal shift clock mode ? external shift clock mode
58 MB90660A series (6) timer input timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) (7) trigger input timing (v cc = +2.7 v to +5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter symbol pin name conditions value unit remarks min. max. input pulse width t tiwh t tiwl tim0 to tim3 4 t cp ns parameter symbol pin name conditions value unit remarks min. max. input pulse width t trgh t trgl at g , dtti, trg, int4 to int7 5 t cp ns at g , dtti, trg, int0 to int3 5 t cp ns 0.7 v cc 0.7 v cc 0.3 v cc 0.3 v cc t tiwh t tiwl 0.7 v cc 0.7 v cc 0.3 v cc 0.3 v cc t trgh t trgl 0.7 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl ? int4 to int7 ? int0 to int3
59 MB90660A series 5. electrical characteristics of a/d converter (av cc = v cc = +2.7 v to +5.5 v, av ss = v ss = 0.0 v, 2.7 v avr, t a = C40c to +85c) *1: v cc = 5.0 v 10% at 16 mhz machine clock *2: v cc = 3.0 v 10% at 8 mhz machine clock *3: current when cpu is stopped and a/d converter is not operating (when v cc = av cc = avr = 5.0 v) notes: ? the relative error becomes larger as the reference voltage (avr) becomes smaller. ? be sure to use the a/d converter only when output impedance of the external analog input circuit meets the following conditions. external circuit output impedance < approx. 7 k w ? if the output impedance of the external circuit is too high, there may not be enough time to sample the analog voltage. (sampling time = 3.75 m s @4 mhz (equivalent to internal 16 mhz when multiplying by 4)) ? for an external capacitor to be provided outside the chip, its capacity should desirably be thousands times larger than of the capacity in the chip taking in consideration the influence of the capacity destribution of the external and internal capacitors. parameter symbol pin name value unit min. typ. max. resolution 10 10 bit total error 3.0 lsb linearity error 2.0 lsb differential linearity error 1.5 lsb zero transition voltage v ot an0 to an7 C1.5 +0.5 +2.5 lsb full-scale transition voltage v fst an0 to an7 avr C 4.5 avr C 1.5 avr + 0.5 lsb conversion time 6.125 *1 m s 12.25 *2 m s analog port input voltage i ain an0 to an7 0.1 10 m a analog input voltage v ain an0 to an7 0 avr v reference voltage avr 3.5 av cc v supply current i a av cc 3 ma i ah av cc 5 *3 m a reference voltage supply current i r avr 200 m a i rh avr 5 *3 m a variation between channels an0 to an7 4lsb comparator analog input r on1 r on2 r on3 c 1 c 0 r on1 = approx. 1.5 k w (v cc = 5.0 v) r on2 = approx. 0.5 k w (v cc = 5.0 v) r on3 = approx. 0.5 k w (v cc = 5.0 v) r on4 = approx. 0.5 k w (v cc = 5.0 v) c 0 = approx. 60 pf c 1 = approx. 4 pf r on4 sample and hold circuit note: use the values shown here as guidelines. ? figure model of analog input circuit
60 MB90660A series 6. definitions of a/d converter terms resolution : analog transition observed with an a/d converter. analog voltage can be divided in 1024 = 2 10 parts at 10-bit resolution. total error : this refers to the difference between actual and logical values. this error is caused by offset errors, gain errors, non-linearity errors and noise. linearity error : deviation of the line drawn between the zero transition point (00 0000 0000 ? 00 0000 0001) and the full-scale transition point (11 1111 1110 ? 11 1111 1111) for the device from actual conversion characteristics. differential linearity error : deviation from ideal input voltage required to shift output code by one lsb. digital output 1111 1111 1111 1110 0000 0001 0000 0000 0000 0010 v ot v nt v (n + 1)t v fst (1lsb n + v ot ) linearity error 1lsb = 1022 v fst ?v ot linearity error = 1lsb v nt ?(1lsb n + v ot ) (lsb) 11 11 00 00 00 1lsb v (n + 1) t ?v nt ?1 (lsb) differential linearity error = analog input
61 MB90660A series n examples characteristics (continued) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 t a = +25? v in ?v cc (hysteresis input) v ihs v ils v oh (v) v cc = 5.0 v i oh (ma) ? 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v oh i oh ? ? ? v cc = 4.0 v v cc = 3.0 v v cc = 2.7 v v cc = 3.5 v t a = +25? v cc = 4.5 v v ol (v) v cc = 5.0 v i ol (ma) 8 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v ol ?i ol 46 2 0 v cc = 3.0 v v cc = 2.7 v v cc = 3.5 v t a = +25? v cc = 4.5 v v cc = 4.0 v v cc = 5.0 v 0 5 15 20 25 10 v ol (v) v cc = 4.5 v i ol (ma) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v ol ?i ol v cc = 4.0 v v cc = 3.0 v v cc = 2.7 v v cc = 3.5 v t a = +25? 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 t a = +25? v in ?v cc (cmos input) (3) l level output voltage (p60 to p65) (4) h level input voltage/l level input volt- age (1) h level output voltage (2) l level output voltage (5) h level input voltage/l level input voltage v ihs : threshold when input voltage in hysteresis characteristics is set to h level v ils : threshold when input voltage in hysteresis characteristics is set to l level
62 MB90660A series (6) power supply current (f cp = internal frequency) (7) pull-up resistor i cc (ma) i cc ?v cc 70 60 50 40 30 20 10 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz i ccs (ma) i ccs ? cc 25 20 15 10 5 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz i a (ma) i a ?av cc 3.0 4.0 5.0 6.0 av cc (v) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = +25? f cp = 16 mhz i r (ma) i r ?avr 3.0 4.0 5.0 6.0 avr (v) 0.30 0.20 0.10 0 t a = +25? f cp = 16 mhz t a = +25? t a = +25? 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1000 r (k w ) v cc (v) 100 10 2.5 t a = +25? r ?v cc
63 MB90660A series n instructions (340 instructions) table 1 explanation of items in tables of instructions item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C:no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
64 MB90660A series table 2 explanation of symbols in tables of instructions (continued) symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al:ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address
65 MB90660A series (continued) table 3 effective address fields note: the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. symbol meaning rel branch specification relative to pc ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
66 MB90660A series table 4 number of execution cycles for each type of addressing note: (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles notes: (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long number of cycles number of access number of cycles number of access number of cycles number of access internal register +0 1 +0 1 +0 2 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +1 1 +4 2 +8 4 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3
67 MB90660A series table 7 transfer instructions (byte) [41 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah /mov @a, t xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
68 MB90660A series table 8 transfer instructions (word/long word) [38 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw al, ah /movw @a, t xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C
69 MB90660A series table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+ (a) 4 6 7+ (a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
70 MB90660A series table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ rg b operation lh ah istnzvc rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
71 MB90660A series table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
72 MB90660A series table 13 logical 1 instructions (byte/word) [39 instructions ] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C *
73 MB90660A series table 14 logical 2 instructions (long word) [6 instructions] table 15 sign inversion instructions (byte/word) [6 instructions] table 16 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah istnzvc rmw neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation lh ah istnzvc rmw nrml a, r0 2 * 1 10 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C
74 MB90660A series table 17 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+ (a) 3 5+ (a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C
75 MB90660A series table 18 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15 (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15 (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
76 MB90660A series table 19 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: retrieve (word) from stack *8: retrieve (long word) from stack *9: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel*9 cwbne ear, #imm16, rel cwbne eam, #imm16, rel*9 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #local8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C
77 MB90660A series table 20 other control instructions (byte/word/long word) [36 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *5: pop count or push count. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
78 MB90660A series table 21 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah istnzvc rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
79 MB90660A series table 22 accumulator manipulation instructions (byte/word) [6 instructions] table 23 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah istnzvc rmw swap swapw/xchw al, ah ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah istnzvc rmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
80 MB90660A series n mask option list notes: ? a specification of yes for accept asynchronous reset input refers to a function whereby reset input is accepted when oscillation for output ports (including peripheral resource output) is stopped and port output (including peripheral resource output) is forced hi-z. note, however, that since internal reset (reset of the cpu and peripheral resources) is synchronized with the clock, the cpu and peripheral resources are not initialized when the clock is stopped. ? for details on writing to the mb90p663a, see chapter 6, n programming the mb90p663a eprom. ? use of a pull-up/pull-down resistors for the mode pins (md2 to md0) can be selected separately for each pin. if yes is selected, a pull-up is attached to md0 and md1 and a pull-down to md2 for mask rom versions. a pull-up is attached to md0 and md1, but a pull-down is not attached to md2 for otp versions. ? since it takes eight machine cycles to make option settings for the mb90p663a, options cannot be set between when power is first turned on and the clock is supplied. (this results in a setting of no pull-up for all pins and accept asynchronous reset input.) no. part number mb60662a mb90663a mb90p663a specifying procedure specify when ordering masking set with eprom programmer 1 p00 to p07 p10 to p17 p20 to p27 p30 to p33 p40 to p47 p60 to p66 rst dtti pull-up resistor can be selected for each pin pull-up resistor can be selected for each pin 2 md2 pull-down resistor can be selected all at once cannot be selected; pull-down resistor not provided md1 pull-up resistor pull-up resistor can be selected all at once md0 pull-up resistor pull-up resistor 3 accept asynchronous reset input accepted not accepted can be selected can be selected
81 MB90660A series n ordering information part number package remarks mb90662ap-sh mb90663ap-sh mb90p663ap-sh 64-pin plastic sh-dip (dip-64p-m01) mb90662apfm mb90663apfm mb90p663apfm 64-pin plastic lqfp (ftp-64p-m09)
82 MB90660A series n package dimensions +0.20 C0.10 +.008 C.004 +0.05 C0.02 +.002 C.001 lead no. (stand off) 64 49 48 33 32 17 16 1 nom (.512) ref (.384) 13.00 9.75 (.012.004) 0.300.10 0.65(.0256)typ 12.000.10(.472.004)sq 14.000.20(.551.008)sq (.020.008) (.004.004) 0.100.10 0.500.20 0 10 details of "a" part "a" 1.50 .059 0.127 .005 1 pin index 0.10(.004) m 0.13(.005) 1994 fujitsu limited f64018s-1c-2 c +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c dimensions in mm (inches) 64-pin plastic sh-dip (dip-64p-m01) dimensions in mm (inches) 64-pin plastic lqfp (fpt-64p-m09)
83 MB90660A series memo
84 MB90660A series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. *ds07-1360 4

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